Odrive 3.6 Schematic [ Linux ]

Executive Summary

The ODrive v3.6 is a capable, cost-effective motor controller, but its schematic reveals a design that straddles the line between "hobbyist accessible" and "industrial robust." It utilizes a mature control architecture but suffers from specific thermal and protection limitations inherent to its compact form factor and component selection. It is a "solid" design for its price point, but it requires respect for its boundaries.

High-Level Block Diagram of the ODrive 3.6

The ODrive 3.6 schematic can be broken into six distinct functional blocks: odrive 3.6 schematic

3. MCU Section (STM32F405)

• U1: STM32F405RGT6
• Crystal (Y1): 8MHz (HSE)
• Debug connector (J4): SWD (PA13, PA14) + UART (PA9, PA10)
• Boot0 switch (SW1): BOOT0 to 3.3V for DFU mode

• Advanced Timers (TIM1, TIM8): Configured for 6-step PWM generation (complementary channels with dead-time insertion) for two independent BLDC motors.
• ADC Channels: At least 3 dedicated analog inputs per motor for phase current sensing (shunt resistors).
• Encoder Interfaces: Multiple TIMx channels configured for quadrature encoder or Hall sensor feedback.
• Communication: CAN transceiver (SN65HVD230), UART for USB bridge (CP2102), and I2C/SPI for external sensors.

Hardware Parity: The main differences between v3.4, v3.5, and v3.6 are minor, such as different filter capacitors or the number of layers in the board. Executive Summary The ODrive v3

• Incremental/absolute encoder connectors, differential input drivers (RS-422/RS-485), index/home signals.

The ODrive v3.6 schematic is essentially an evolution of the v3.5 design. It is built around a dual-motor control architecture, allowing a single board to drive two brushless DC (BLDC) motors with high precision. Core Controller : It utilizes an STM32F405RGT6 U1 : STM32F405RGT6 Crystal (Y1) : 8MHz (HSE)